1. Field of Invention
This invention relates to an integrated circuit (IC) process, and particularly to a method for forming separate narrow lines, a method for fabricating a memory structure based on the former method, and a memory structure fabricated based on the methods.
2. Description of Related Art
The resolution in a photolithography process depends on the wavelength of the exposure light, the numerical aperture (NA) of the optical system and the design of the photomask, and therefore has a certain limit. When the resolution required by target patterns exceeds the lithographic resolution, for example, in a case of forming the gate line array of a high-density memory like a high-density flash memory, a pitch reduction method is needed, which may be based on the spacer forming technique.
For example, separate narrow lines beyond the lithographic resolution may be formed using the so-called self-aligned double patterning (SADP) technique. After a target layer is formed, base line patterns are defined over the same by lithography. Spacers of a smaller width/pitch are formed on the sidewalls of the base line patterns as target line patterns and connection patterns therebetween, and then the base line patterns are removed. Each connection pattern is partially or entirely removed using a specific lithographically defined mask layer to disconnect the target line patterns, and then the disconnected target line patterns are transferred.
Accordingly, the method is tedious as requiring two lithographic processes.